Display system with frame reuse using divided multi-connector element differential bus connector

ABSTRACT

A method includes reducing power of a first graphics processor by disabling or not using its rendering engine and leaving a display engine of the same first graphics processor capable of outputting display frames from a corresponding first frame buffer to a display. A display frame is rendered by a second graphics processor while the rendering engine of the first graphics processor is in a reduced power state, such as a non-rendering state. The rendered frame is stored in a corresponding second frame buffer of the second graphics processor, such as a local frame buffer and copied from the second frame buffer to the first frame buffer. The copied frame in the first frame buffer is then displayed on a display while the rendering engine of the first graphics processor is in the reduced power state. Accordingly thermal output and power output is reduced with respect to the first graphics processor since it does not do frame generation using its rendering engine, it only uses its display engine to display frames generated by the second graphics processor.

RELATED CO-PENDING APPLICATIONS

This application is a divisional application of co-pending applicationSer. No. 11/955,783, filed on Dec. 13, 2007, entitled “DISPLAY SYSTEMWITH FRAME REUSE USING DIVIDED MULTI-CONNECTOR ELEMENT DIFFERENTIAL BUSCONNECTOR” having inventors James Hunkins et al., owned by instantAssignee which is related to co-pending application Ser. No. 11/955,798,filed on Dec. 13, 2007, entitled “ELECTRONIC DEVICES USING DIVIDED MULTICONNECTOR ELEMENT DIFFERENTIAL BUS CONNECTOR”, having inventors JamesHunkins et al, owned by instant Assignee and is incorporated herein byreference; and is related to co-pending application Ser. No. 12/941,157filed Nov. 8, 2010, entitled “ELECTRICAL CONNECTOR, CABLE AND APPARATUSUTILIZING SAME”, having inventor James Hunkins, owned by instantAssignee and is incorporated herein by reference which is a continuationof co-pending application Ser. No. 11/955,760, filed on Dec. 13, 2007,entitled “ELECTRICAL CONNECTOR, CABLE AND APPARATUS UTILIZING SAME”,having inventor James Hunkins, owned by instant Assignee and isincorporated herein by reference.

FIELD OF THE INVENTION

The disclosure relates to electronic devices, that employ connectorsthat communicate differential signals.

BACKGROUND OF THE INVENTION

Electronic devices such as laptops, desktops, mobile phones and otherdevices may employ one or more graphics processing circuits such as agraphics processor (e.g. a graphics core co-located on a dye with a hostCPU, separate chip coupled to a mother board, or located on a plug-incard, a graphics core integrated with a memory bridge circuit, or anyother suitable configuration) to provide graphics data and/or videoinformation, video display data to one or more displays.

One type of communication interface design to provide the necessary highdata rates and communication performance for graphics and/or videoinformation between a graphics processor and CPU or any other devices isknown as a PCI Express™ interface. This is a communication link that isa serial communications channel made up of sets of two differential wirepairs that provide for example 2.5 MBytes per second (Gen 1) or 5.0MBytes per second (Gen 2) in each direction. Up to 32 of these “lanes”may be combined in times 2, times 4, times 8, times 16, times 32configurations, creating a parallel interface of independentlycontrolled serial links. However, any other suitable communication linkmay also be employed. Due to the ever increasing requirements ofmultimedia applications that require the generation of graphicsinformation from drawing commands, or a suitable generation of videoputs increasing demands on the graphics processing circuitry and system.This can require larger integrated graphics processing circuits whichgenerate additional heat requiring cooling systems such as activecooling systems such as fans and associated ducting, or passive coolingsystems in desktops, laptops or other devices. There are limits to theamount of heat that can be dissipated by a given electronic device.

It has been proposed to provide external graphics processing in aseparate device from the laptop, desktop or mobile device to allowfaster generation of graphics processing through parallel graphicsprocessing operations or to provide output to multiple displays usingexternal graphics devices. However, since devices are becoming smallerand smaller there is an ever increasing need to design connections,including connectors and cabling that allow proper consumer acceptanceand suitable speed and cost advantages. Certain video games for examplemay require high bandwidth graphics processing which may not beavailable given the cost, integrated circuit size, heat dissipation, andother factors available on a mobile device or non-mobile device.

From an electrical connector standpoint, for years there have beenattempts by various industries to design connectors that provide therequisite bandwidths such as the multiple gigabytes necessary tocommunicate video frame information and/or graphics information betweendevices. One proposal has been to provide an external cable and circuitboard connector that uses for example a 16 lane configuration forPCI-e™. This proposal results in a printed circuit board footprint ofapproximately 40.3 mm×26.4 mm and a connector housing depth profile 40.3mm×11.9 mm which includes the shell depth and housing of the connector.However, such large connectors have only been suitable for largerdevices such as servers which can take up large spaces and can be manypounds in weight. For the consumer market such large connectors are toolarge and costly. A long felt need has existed for a suitable connectorto accommodate multiple lanes of communication to provide the necessarybandwidth for graphics and video information.

Other connectors such as Display Port™ connectors are limited to onlyfor example two lanes, although they have smaller footprints they cannotsupport the PCI-e™ express cable specification features and have limitedcapabilities. Other proposals that allow for, for example a 16 lanePCI-e™ connection have even larger footprints and profiles and mayemploy for example 138 pin total stacked connector to accommodate 16lanes (VHDCI). The size of the footprint and profile can be for examplein excess of 42 millimeters by 19 millimeters for the footprint and inexcess of 42 by 12 millimeters in terms of the PCI-e™ board profile thatthe connector takes up. Again, such connectors require the size of themobile device or laptop device to be too large or can take up anunreasonable amount of real estate on the PC board or device housing toaccommodate the size of such large connectors. In addition, suchconnectors also utilize large cabling which can be heavy and cumbersomein use with laptop devices. The costs can also be unreasonably high. Inaddition, motherboard space is at a premium and as such largerconnectors are not practical.

From an electronic device perspective, providing external graphicsprocessing capability in a separate device is also known. For example,docking stations are known that employ a PCI-e™ express interfaceconnector that includes a single lane to communicate with the CPU in forexample a laptop computer that is plugged into the docking station. Thedocking station includes its own A/C connector and has additionaldisplay connector ports to allow external displays to be connecteddirectly to the docking station. The laptop which may have for exampleits own LCD display and internal graphics processing circuitry in theform of an integrated video/graphics processing core or card, utilizesthe laptop's CPU to send drawing commands or compressed video via thesingle lane PCI-e™ express connector to the external graphics processorlocated in the docking station. However, such configurations can be tooslow and typically employ a low end graphics processor since there isonly a single lane of communication capability provided.

Other external electronic units that employ graphics processingcircuitry to enhance the graphics processing capabilities of a desktop,laptop or other device are also known that employ for example a signalrepeater that increases the signal strength of graphics communicationsacross a multilane PCI-e™ connector. However, the connector is a largepin connector with large space in between pins resulting in a connectorhaving approximately 140 pins if 16 lanes are used. The layoutrequirements on the mother board as well as the size of the connectorsare too large. As a result, actual devices typically employ for examplea single lane (approximately 18 pin connector) connector including manycontrol pins. As such, although manufacturers may describe wanting toaccommodate multilane PCI-e™ express communications, practicalapplications by the manufacturers typically result in a single laneconfiguration. This failure to be able to suitably design andmanufacture a suitably sized connector has been a long standing problem.

Other external devices allow PCI-e™ graphics cards to be used innotebooks. Again these typically use a single lane PCI-e™ expressconnector. Such devices may include a display panel that displaysinformation such as a games current frame rate per second, clock speedand cooling fan speed which may be adjusted by for example a functionknob or through software as desired. A grill may be provided for exampleon a rear or side panel so that the graphics card may be visible insideand may also provide ventilation. The internal graphics card may beover-clocked in real time by turning a control knob for example toattempt to increase performance of the external graphics processingcapability. However, as noted, the communication link between the CPUand the laptop and the external electronic device with the graphics cardtypically has a single PCI-e™ express lane limiting the capability ofthe graphics card.

Also, systems that use multiple graphics processors such as graphicsprocessor cores that are included as part of a Northbridge circuit, CPU,or any other circuit and can generate or render frames based on drawingscommands and/or video processing commands. As known in the art drawingcommands may be, for example, 3D drawing commands and video processingcommands may be commands to decode compressed video or otherwise processvideo as known in the art. Such systems can generate undesirable amountsof thermal output and consume undesirable amounts of power. A knownsystem attempts to utilize multiple graphics processors to speed upprocessing to improve performance for a user. For example, a graphicsprocessor (e.g., core with one or more pipelines) is used to provide andgenerate one frame for display while another graphics processor is usedto generate another frame. Multiplexing circuitry is then used to outputa rendered frame from a respective frame buffer corresponding to each ofthe differing graphics processors. However, such rendering is typicallydone in parallel. In another system, a host graphics processor and itscorresponding frame buffer receives a copy of a frame that has beenrendered by another graphics processor and stores the copied frame inits local frame buffer. However while the host GPU is using its displayengine to display the frame from its local frame buffer that was copiedinto it by the other graphics processor, it is also using its renderingengine to render portions of another frame in parallel with the remotegraphics processor. As such, such systems attempt to provide renderingin parallel thereby increasing the processing capability of the systembut also increasing the power usage and thermal output generated.

Also, there is a need to reduce heat produced and power consumed bygraphics processors (e.g., cores) in devices such as laptops, handhelddevices, desktops and other devices with one or more graphics processorstherein.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more readily understood in view of the followingdescription when accompanied by the below figures and wherein likereference numerals represent like elements, wherein:

FIG. 1 is a perspective view illustrating one example of an electricalconnector in accordance with one example set forth in the disclosure;

FIG. 2 is a cross sectional view of the connector of FIG. 1;

FIG. 3 illustrates one example of upper and lower rows of contacts usedin the connector of FIG. 1;

FIGS. 4 and 5 diagrammatically illustrate signaling configurationsprovided by the connector of FIG. 1 according to one example set forthin the disclosure;

FIG. 6 is a perspective view illustrating one example of a cableconnector that mates with the connector of FIG. 1 in accordance with oneexample set forth in the disclosure;

FIGS. 7-14 are diagrams illustrating signaling provided by theelectrical connector of FIG. 1 and cable connector of FIG. 6 in anelectronic device or system in accordance with one disclosure set forth;

FIGS. 15-18 are diagrams illustrating signaling provided by theelectrical connector of FIG. 1 and cable connector of FIG. 6 in anelectronic device or system in accordance with one disclosure set forth;

FIGS. 19-24 are diagrams illustrating signaling provided by theelectrical connector of FIG. 1 and cable connector of FIG. 6 in anelectronic device or system in accordance with one disclosure set forth;

FIG. 25 diagrammatically illustrates a system employing frame reuse inaccordance with one example set forth in the disclosure;

FIG. 26 illustrates one example of an electronic device that includes atleast one electrical connector described herein and a plurality ofelectronic circuit substrates each containing graphics processors inaccordance with one example;

FIG. 27 diagrammatically illustrates an electronic device that employsat least one of the connectors described herein and active coolingmechanism to cool graphics processing circuitry in accordance with oneexample described herein;

FIG. 28 diagrammatically illustrates the device of FIGS. 26 and 27;

FIG. 29 is a block diagram illustrating one example of an electronicdevice that facilitates card plug-in of a plurality of plug-in cards inaccordance with one embodiment described herein;

FIG. 30 illustrates a block diagram of a system that employs a hubdevice in accordance with one example described herein; and

FIG. 31 is a flow chart illustrating one example of a method ofrendering frames and displaying frames using a plurality of graphicsprocessors in accordance with one example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Briefly, in one example a method includes reducing power of a firstgraphics processor by turning off its rendering engine and leaving itsdisplay engine capable of outputting display frames from a correspondingfirst frame buffer to a display. A display frame is rendered by a secondgraphics processor while the rendering engine of the first graphicsprocessor is turned off or otherwise unused. The rendered frame isstored in a corresponding second frame buffer of the second graphicsprocessor, such as a local frame buffer and copied from the second framebuffer to the first frame buffer. The copied frame in the first framebuffer is then displayed on a display while the rendering engine of thefirst graphics processor is in the reduced power state. Among otheradvantages the thermal output and power output is reduced with respectto the first graphics processor since it does not do frame generationusing its rendering engine, it only uses its display engine to displayframes generated by the second graphics processor. A correspondingapparatus and system is also disclosed.

For example, an electronic device is disclosed that includes a housingthat includes an A/C input or DC input, and at least one circuitsubstrate that includes electronic circuitry, such as graphicsprocessing circuitry (e.g., that performs video/graphics processing asknown in the art such as MPEG compression/decompression, 3D graphicsrendering based on drawing commands etc.) that receives power based onthe A/C input or DC input. The electronic device also includes a dividedmulti-connector element differential bus connector that is coupled tothe electronic circuitry. The divided multi-connector elementdifferential bus connector includes a single housing that connects withthe circuit substrate and the connector housing includes therein adivided electronic contact configuration that includes a first group ofelectrical contacts divided from an adjacent second group of mirroredelectrical contacts wherein each group of electrical connects includes arow of at least lower and upper contacts. The device uses it's graphicsprocessing circuitry and a local frame buffer to render an image for aremote device. The rendered image is stored in the local frame bufferand is sent and copied to the remote device's frame buffer via thedivided multi-connector element differential bus connector. The remotedevice's display engine then displays the copied image from its ownframe buffer on a display. No rendering need be done by the remote unitso minimal power is consumed by the remote unit.

Drawing commands to render graphics, compressed video for processing orother data for processing is sent from the remote device (e.g., hostdevice) to the electronic device as downstream data via a dividedmulti-connector element differential bus connector on the remote device.Frames are produced and communicated upstream via the same differentiallanes from the electronic device to the remote device via the dividedmulti-connector element differential bus connectors (and cable) suchthat, in one example, saturation of the lanes connected to the connectoris avoided by sending only the number of frames that make up a maximumremote device display rate. This may done by peer to peer readstriggered directly from the remote device or using any suitable displayrefresh synchronization schemes known in the art.

Also in one example, the electronic device housing includes air flowpassages, such as grills, adapted to provide air flow through thehousing. The electronic device housing further includes a passive oractive cooling mechanism such as a fan positioned to cool the circuitryduring normal operation. In one example, the electronic device does notinclude a host processor and instead a host processor is in a separateelectronic device that communicates with the graphics processingcircuitry through the divided multi connector element differential busconnector. In another example, a CPU (or one or more CPUs) is alsoco-located on the circuit substrate with the circuitry to provide a typeof parallel host processing capability with an external device.

In one example, the electronic circuitry communicates with a processor,such as a CPU, in another electronic device external to the housing ofthe electronic device and the graphics processing circuitry receivesdrawing commands from the external processor and communicates displaydata to a display that is coupled to the electronic device. In oneexample, the housing includes air ducting between the active coolingmechanism and the electronic circuitry. In one example, the dividedmulti-connector element differential bus connector provides drawingcommands to the graphics processing circuitry from, for example, theprocessor located in the other electronic device. The divided multiconnector element differential bus connector may be a unique 16 lane PCIExpress™ type bus connector to provide high speed video and/or graphicsinformation between electronic devices.

In one example, the electronic device includes power up control logic,such as a switch, that is operatively coupled to the divided multiconnector element differential bus connector that waits to power up thegraphics processing circuit until after the external device is poweredup as detected from a signal from the divided multi connector elementdifferential bus connector.

In another example, the electronic device includes a plurality ofprinted circuit boards each including graphics processing circuitrythereon and wherein each of the plurality of printed circuit boards iscoupled to the divided multi connector element differential busconnector and wherein the graphics processing circuitry provide parallelor alternate graphics processing operations for a given display frame.

In another example, the circuit substrate includes electronic circuitryand a bus bridge circuit. A backplane is coupled to the bus bridgecircuit that includes a plurality of card ports that are each configuredto receive a plug-in card.

In another example, an electronic device does not utilize A/C powerinput but instead gets limited amounts of D/C power from anotherexternal device through a suitable connector. In one example, theelectronic device includes a housing that includes a circuit substratethat includes a bus bridge circuit and a plurality of divided multiconnector element differential bus connectors each coupled to the busbridge circuit and each including a single connector housing with thedivided electrical contact configuration. The bus bridge circuit iscoupled to receive power from an external device connected to at leastone of the plurality of bus connectors.

In one example, the divided multi-connector element differential busconnector includes a housing having therein a divided multi-connectorelement. The electrical connector is adapted to electrically connectwith a substrate, such as a circuit board. The divided multi-connectorelement includes a divided electrical contact configuration thatincludes a first group or subassembly of electrical contacts physicallyseparate from an adjacent and second group or subassembly of contacts.The first group of electrical contacts and second group of electricalcontacts each include a row of lower contacts and upper contacts. Thesecond group of electrical contacts has an identical but mirroredconfiguration (e.g., with respect to a vertical axis) as the first groupof electrical contacts.

In one example, the electrical connector housing is sized to provide asubstrate footprint of approximately 12 mm×53 mm and has a profile ofapproximately 53 mm×6 mm and includes 124 pins configured for a 16 lanedifferential bus. The 16 lanes are divided into two 8 lane pingroupings. Also in one example, the first and second group of contactsinclude an end grounding contact wherein a respective end groundingcontact is positioned adjacent to another end grounding contact in theother group and are located substantially in the center of the connectorhousing. Also in one example, rows of upper contacts are surface mountpins and rows of lower contacts are through hole pins that pass throughthe substrate.

An electrical device is also disclosed that employs the above mentionedelectrical connector and has an electronic circuit substrate coupled tothe electrical connector and also includes electronic circuitry locatedon the electronic circuit substrate that is coupled to the first andsecond group of electrical contacts. The electronic circuitry provides aplurality of differential data pair signals on either side of a centerportion of the connector and also provides differential clock signals ina center portion of the first group of electrical contacts. The firstrow of upper contacts are used to provide control signals associatedwith the differential pair signals.

The second group of contacts are coupled such that the second row oflower contacts includes a plurality of differential data signals thatare provided on adjacent pins separated by differential ground. A cableis also disclosed that has same end connectors that mate with theelectrical connectors. In one example, the cable assembly has a 16 laneconnector on one end and an 8 lane connector on the other, adapted toelectrically mate with only the first group of electrical contacts inthe 16 lane connector and not the second group of electrical contactsthereby allowing a 16 lane board connector to be used to connect to an 8lane unit.

One of the many advantages of the disclosed connector or cable orelectronic device include the providing of a compact connector thatprovides high speed communication via a multilane differential signalingbus, such as a PCI Express™ compatible bus or interface. Additionally,an 8 lane connector may also be suitably connected with a 16 pin boardconnector via an 8 lane cabling system since a group of contacts andelectronic circuitry provides the necessary data clock signal through asingle grouping of contacts.

Referring to FIGS. 1 and 2, one example of an electrical connector 100that may be coupled to a circuit substrate, such as a printed circuitboard, includes a substrate positioning or locating pin 102 and a shellor housing connection post 104. The positioning pin 102 and housingconnection post 104 are configured to pass through holes that have beendrilled in the circuit substrate and facilitate the mounting of theelectrical connector to the substrate. The electrical connector 100includes a housing 106 that includes a divided multi-connector element108 that is adapted to electrically connect with a circuit substrate,via for example separate subassemblies of contact pins. The dividedmulti-connector element 108 includes a divided electrical contact pinconfiguration that includes a first group or subassembly of electricalcontacts 110 that are physically separate or disconnected from anadjacent and second group or subassembly of contacts 112.

Referring also to FIG. 3, the first group of electrical contacts 110includes a row of lower contacts 114 and a row of upper contacts 116.Similarly, the second and separate group of electrical contacts 112includes an identical but mirrored configuration as the first group ofelectrical contacts and as such, has identical and mirrored but separatecorresponding rows of lower contacts 118 and upper row of contacts 120.In this example, the first group of electrical contacts 110 form acomplete 8 lane PCI Express™ communication interface when coupled to aPCI Express™ transceiver circuit, such transceiver circuits are known inthe art. The rows of lower contacts 114 and 118 separate subassembliesand are through hole pins in this example. They are coupled in anelectronic device to include and provide connection with differentialreceivers or transceivers (see for example, FIGS. 7-14). The groups oftop rows of contact pins 116 and 120 are surface mount pins which mountto a surface of the circuit substrate, and are coupled to an electroniccircuit to provide differential transmission signals. In this example, a16 lane PCI Express™ compatible connection can be facilitated in a smallprofile and relatively inexpensive connector design. Each separategroupings of contacts are electronically connected to each provide 8lanes of differential signaling based communication resulting in the 16lane communication bus.

Referring back to FIG. 1, the housing 106 may be made of any suitablematerial including insulating plastic or any suitable composite materialas known in the art. The electrical contacts may also be made of anysuitable material such as copper alloys with suitable plating such asgold plating over nickel or any other suitable material and finish asdesired. The lower row of contacts 114 in the first group are fabricatedas a separate set of lower row of pins and serves as a subassembly ofthe connector 100. Lower row of contacts 118 are an identical andmirrored subassembly and separate from the lower row of contacts 114.Similarly, the upper row of contacts 116 and 120 are configured asseparate assemblies each identical and mirrored to one another. In thisexample, a total of four sets of pins are used to provide the twogroupings of upper and lower contacts. Among other advantages, theseparation of the lower and upper contacts into separate subassembliescan help reduce the number of pins required to provide the signalingrequired for a 16 lane or 8 lane PCI Express™ type bus. Other advantageswill be recognized by those of ordinary skill in the art.

Also as shown in this example, the spacing between the surface mountpins may be, for example, 0.7 mm and the width of a surface mount pinmay be, for example, 0.26 mm however any suitable spacing and width maybe used. The through hole pins may have a spacing of, for example, 0.7mm (and as shown in FIGS. 4 and 5), may be offset. In addition, thewidth of the through hole pins may be, for example, 0.74 mm. However,any suitable sizing may be employed as desired.

With the 16 lane PCI Express™ compatible configuration, the housing 106is sized to provide a substrate footprint of approximately 12 mm×53 mmsuch that the housing may have, for example, a 12.2 mm depth and a 53.25mm width, or any other suitably sized dimensions. For example, the depthand width may be several millimeters larger or smaller as desired. Alsoin this example, the rows of lower and upper contacts for both the firstand second group of electrical contacts include 124 pins configured fora 16 lane PCI Express™ interface (e.g., two 8 lane differential buslinks).

The connector 100 as shown may include one or more friction tabs 116that frictionally engage a cable connector that mates with the boardconnector 100. Other known connector engagement features may also beemployed such as openings 118 and 120 that receive protrusions thatextend from a corresponding mating cable connector.

Referring again to FIG. 2, the connector 100 may include as part of thehousing, insulation covering 202 and ground contacts and frictionallocks 206 and 208 that frictionally engage with a mating cable connectorusing techniques known in the art. Supporting structures 210 are alsoemployed to support pins in their appropriate positions within theconnector using known techniques. The connector 100 includes a centersupport structure 212 over which the upper rows of surface mount pins116 are supported and over which lower contacts 114 are also supported.The center support structure 212 supports the electrical contacts and inoperation receives a mating connector whose contacts align with theupper and lower contacts 114 and 116 to make electrical contact.

FIGS. 4 and 5 diagrammatically illustrate a portion of a printed circuitsubstrate referred to as a substrate layout showing surface mountcontacts 400 and through holes 402 that are positioned on a circuitsubstrate. The lower rows of contacts 114 and 118 are coupled to thethrough holes 402 to provide electrical contact and signal communicationthrough the connector 100 to an electrical circuit or circuits on theprinted circuit board. Traces or pins from an electrical circuit may beelectrically coupled to the pads 400 to communication signals throughthe connector 100. The figure shows a pinout of the bottom row contactsof connector 100 and the electronic signals designated as 406 and 408corresponding to respective contacts in the connector 100.

In this example, groupings of contacts form upper 8 lanes shown as 410and a lower 8 lanes designated 412. Electronic circuitry 414, such as aPCI Express™ 16 lane interface circuit that may be integrated in agraphics processor core, CPU, bridge circuit such as a Northbridge,Southbridge, or any other suitable bridge circuit or any other suitableelectronic circuit sends and receives signals identified as 406 and 408via the connector 100. Electronic circuitry 14 is located on theelectronic circuit substrate and is coupled to the first group ofelectrical contacts and second group of electrical contacts (shown hereare only the lower contacts). The electronic circuitry 414 providesdifferential clock signals labeled 416 and 418 that are located in acenter portion of the first group of contacts 110. The electroniccircuitry also provides a plurality of differential data pair signalsgenerally designated as 420 on either side of a center portion 421.Corresponding differential ground signals 424 are provided between thedifferential signals 420. Upper contacts 116 (not shown) provide controlsignals associated with the differential data pair signals 420. In thisexample, the other group of contacts 112 does not include thedifferential clock signals 416 and 418. The electronic circuitryprovides all of the necessary PCI Express™ type control signaling, clocksignaling and power to run an 8 lane bus via the first grouping ofcontacts 110. 16 lanes may be accommodated by providing the signaling asshown. This incorporates utilizing the second group of contacts 112.

As also shown, the first group of electrical contacts 110 and secondgroup of electrical contacts 112 are divided by adjacent ground contactsdesignated 426 and 428. The second group of contacts 112 are coupledsuch that the second row of lower contacts include a plurality ofdifferential data signals 430 that are provided on adjacent pinsseparated by corresponding differential ground signals 432 and power isprovided on an outer pin portion designated as 434 to a second row oflower contacts. Similarly, power is provided on an outer portion of theconnector corresponding to the first group of contacts 114 shown aspower signals 436. In this example, the electronic circuitry 414includes differential multilane bus transceivers that are PCI Express™compliant, as known in the art. However, any suitable circuitry may becoupled to the connector 100 as desired. As also shown, the first andsecond group of contacts 110 and 112 each include the end groundingcontact 426 and 428 that are positioned adjacent to each other andsubstantially in the center of the housing.

In addition, the first and second groups of electrical contacts includesensing contacts positioned at an outer end of a row of contacts todetermine proper connector insertion on both ends of the cable. Inaddition, the connector also includes a power control pin that can beused in conjunction with the sensing contacts to control powersequencing and other functions between the two connected systems.

FIG. 6 illustrates one example of a cable having a cable end connector500 that is configured to matingly engage with the connector 100. Thecable 502 includes an end connector on either end thereof (although notshown) that are identical to the end connector 500 and the connector end500 is adapted to mate with the divided multi-connector element 108. Assuch, the cable end connector 500 also includes a male portion 504 thatengages with the contacts via center portion 212 of connector 100. Asknown in the art, the end connector may be made of any suitablematerials including plastic and metal to provide the necessarystructural, shielding and grounding characteristics as desired. The maleportion 504 is adapted to frictionally engage with the friction tabs 116of the board connector 100. The cable 502 may be made of two groups ofwires each forming an 8 lane grouping. However, any suitableconfiguration may be used.

FIGS. 7-14 illustrate a diagram illustrating electrical signals that areprovided by the electrical circuitry 414 through connector 100 in onedevice and corresponding electrical circuitry that is in another devicethat is connected via the cable connector 502. As such, a host device(referred to as host side), such as a laptop computer or any othersuitable device is connected via a cable to a downstream device via aconnector 100 and the downstream device also contains the connector 100.As such, a simplified connector/cable pairing is suitably provided withhigh speed data communication capability. As illustrated, the connector100 is operatively coupled to electronic circuitry to provide thesignals on the pins as shown. As a point of reference, a portion ofFIGS. 4 and 5 showing the signals is duplicated in FIGS. 7-14 shown byarrow 600. The top row of contacts 116 and 120 are shown by the portionlabeled 602. As shown, the bottom rows of contacts 114 and 118 areprimarily coupled between differential transmitters of for example agraphics processor (downstream device) and differential receivers of thehost device whereas the top rows 116 and 120 of connector 100 arecoupled between receivers of the graphics processor located in adownstream device and differential transmitters of a host device.

In the host device, the corresponding lower rows 114 and 118 shown as604 are provided as shown. For example, a top row 116 and 120 on a hostside device shown as signals 606 are provided by suitable electroniccircuitry. In this example, the circuitry as noted above includes PCIExpress™ compliant interface circuitry that provides in this example 16lanes of information. The total number of pins used in this example is124 pins. As such, this reflects a signal and pinout for a 16 lane to 16lane connection.

FIGS. 15-18 illustrate instead, a signal and pinout configuration for an8 lane to 8 lane connection using instead of a 16 lane sized connector,an 8 lane size connector. However, the identical signals are provided onthe identical pins of the 8 pin connector as are provided on the firstgroup of connectors 110 of the 16 lane connector. As such, an 8 laneconnector may be employed that is similar in design to the connectorshown in 100 except that half of the pins are used resulting in ahousing that is sized to provide a footprint of approximately 12 mm×32mm and a profile of approximately 32 mm×6 mm and includes a total of 68pins configured in a row of lower contacts and upper contacts. As such,FIGS. 15-18 illustrate a host side connector 702 that is connected witha downstream device connector 704 via an 8 lane cable 706.

FIGS. 19-24 illustrate yet another configuration that employs pinout andsignaling wherein a first device such as a host device employs an 8 laneconnector with signaling shown as 702 with a cable that at another endincludes the connector 100 with the pinout and signaling shown as 600and 602. As such, an 8-16 lane connector configuration may be usedwherein only 8 lanes of the 16 lane connector are actually coupled tocircuitry. In this manner, existing 16 lane connectors may be readilycoupled to devices that employ 8 lane connectors if desired.

FIG. 25 illustrates one example of a system 900 that employs a firstdevice 902, such as a host device such as a laptop, desktop computer orany other suitable device and a second device 904 such as a deviceemploying an electronic circuit that includes electronic circuitry 414operatively mounted to substrate 908 such as a printed circuit boardthat contains connector 100. The electronic circuitry 414 may be, forexample, a graphics processor or any other suitable circuitry and inthis example includes PCI Express™ compliant transceiver circuitry tocommunicate with the host device 902 via the cable and connectorstructure described herein. The device 904 which may include, forexample, a housing that includes grates that serve as air passages 910that provide air flow for cooling the electronic circuitry and may alsoinclude an active cooling mechanism such as a fan 913 although suitablycontrolled to provide cooling via air flow, as known in the art. Thesubstrate 908 may include a power supply circuit 912 that provides asuitable power for all electronic circuitry and may receive alternatingcurrent (AC) from an outlet through plug 914. The host device mayinclude as known, one or more central processing units 920 and one ormore graphics processors 922 in addition to suitable frame buffer memory923, operating system software and any other suitable components,software, firmware as known in the art. As such, in this example, thedevice 904 may receive drawing commands from the CPU 920 and/or GPU 922via the differential signaling provided through the connectors 100 andcabling 502 to provide off device graphic processing enhancement througha suitable connector arrangement that is consumer friendly, relativelylow cost and provides the data rates required for a high data ratevideo, audio and graphics processing.

The electronic circuitry 414 as noted above may include graphicsprocessing circuitry such as graphics processor core or cores, one ormore CPUs, or any other suitable circuitry as desired. As shown, in thecase that the electronic circuitry includes graphics processingcircuitry, one or more local frame buffers 930 are accessible by thegraphics processing circuitry through one or more suitable buses 932 asknown in the art. Also, in another embodiment, where a single circuitsubstrate 908 is used, the electronic circuitry 414 may include aplurality of graphics processing circuits such as a plurality ofgraphics processors 933 and 934 that are operatively coupled via asuitable bus 936 and may be connected with the divided multi-connectorelement differential bus connector 100 via a bus bridge circuit 938 suchas a PCI bridge, or any other suitable bus bridge circuit. The busbridge circuit provides information to and from the connector 100 andalso switches communication paths between the connector 100 and each ofthe graphics processors 932 and 936 as known in the art. As such, inthis example, a plurality of graphics processors, for example, canprovide parallel or alternate graphics processing operations for thehost device 902 or other suitable device.

FIG. 26 diagrammatically illustrates one example of the device 904 in ahousing 1000 that includes air flow passages shown as 1002, 1004 and1006. In this example, the air flow passages are grills that provide airflow through the housing. The active air cooling mechanism 912 is shownas being a plurality of individual fans 1010 and 1012 that providecooling for a plurality of printed circuit boards 908 and 1014 (e.g.,cards) that may contain, for example, graphics processors, multimediaprocessors, CPUs, or any suitable electronic circuitry. Also referringto FIG. 28, in this example, each of the cards 908 and 1014 areconnected by either separate standard PCI-E connectors 1220 and 1222 (ora board to board version of the divided multi-connector elementdifferential bus connectors 400) on a backplane card 1224 which holds aPCI-E bridge which connectors the two cards to a separate divided multiconnector element differential bus connector 100 (see for example, FIGS.4 and 5).

Graphics card brackets 1020 and 1022 hold connectors for externalmonitors. In this example, no CPU is employed in the device 904 and inthis example the device is used as a type of external graphicsenhancement device. Also in this example, ducting such as plasticpassages designated as 1030 direct air flow over the elements to becooled on the printed circuit boards or cards 908 and 1014. In addition,the power supply may also include a separate fan designated 1032.However, it will be recognized that any single fan for all coolingoperations or multiple fans may be used as desired.

Referring to FIGS. 27 and 28, there may also be ducting to direct airflow from a grill to a fan as shown by ducting 1200. As also shown, thecards 908 and 1014 are separated to provide thermal convection asdesired. Also shown as part of the power supply is an on/off switch1040. The power supply may receive an A/C input such as an A/C signalfrom an outlet and convert the A/C to DC or may receive a DC inputsignal from a DC power source. In this example, the cards 908 and 1014have in this example, PCI edge connectors at a bottom thereof 1220 and1222 (see FIG. 28) that connect with a backplane 1224 that, in thisexample, lies horizontally beneath the cards 908 and 1014. The backplaneincludes connectors that mate with the card edge connector. The busbridge circuit 938 acts as a switch to route information from theconnector 100 to either or both of the cards 908 and 1014.

It will be recognized that many usage scenarios are possible. Forexample, a circuit board with one or more graphics processors forexample may be utilized to upgrade a remote host system, that may alsohave one or more graphics processors therein depending upon performancerequirements. Each graphics processor may be individually coupled to aconnector 100 or each graphics processor may use, for example, 8 lanesof a single connector as desired or share all 16 lanes through a PCI-Eswitch device. In addition, portable devices such as laptops may enhancetheir graphics processing or video processing capability or otherprocessing capabilities, if desired, since thermal limits and powerlimits are reduced due to the separate electronic device. As such, asused herein, graphics processing circuitry can include video processingsuch as video coding and decoding circuits, high definition televisionimage processing, or any other suitable video processing or multimediaprocessing operations as desired. It will be appreciated that externaldevices that may connect to the electronic device 904 for example mayinclude set top boxes, televisions, game consoles, handheld devices,laptops, desktops, or any other suitable device as desired. In addition,one or more displays such as LCD displays may also be connected to thedevice 904. Display ports may be utilized so that separate displays maybe plugged into the electronic device 904 so that the output from thegraphics processors therein can be displayed on one or more display (seeFIG. 25). Alternatively, the graphics processor within the device 904may send frame information or any other information back to the hostdevice which may then use its own display capabilities to output theinformation on a different display.

Referring also to FIGS. 7-14, the CPWRON signal comes from the hostdevice across the connector 100 indicating when, for example, theexternal device is powered up and active (a non-standby mode). Theelectronic circuitry in the device 904 then detects a CPWRON signal andpowers up. The CPRSNT pins are used to detect full connection of thedevice 904 to an external device such as a host system to both help gatethe power on of the device 904 and to notify the host system that theexternal device 904 is connected and powered. Two pins are used in oneexample to ensure that the connector 100 is fully seated beforenotifying the host system that it is available. In addition, a hot plugmechanism may also be utilized to detect when the device 904 isconnected to another external device.

FIG. 29 illustrates another example of an electronic device 1300 thatincludes a circuit substrate 1302 that includes a bus bridge circuit1304 that is coupled to the connector 100 and is coupled to bus slotports 1306 and 1308. The bus slot ports 1306 and 1308 need not beconnector 100 but may be, for example, PCI Express™ slots that receivePCI Express™ cards 1310 and 1312 that may include any suitableelectronic circuitry thereon. The bus slot ports 1306 and 1308 may bemounted on an active backplane for example. The active backplane may bean active backplane card to facilitate easy connection with the busbridge circuit 1304. The active backplane card includes the plurality ofcard ports 1306 and 1308 that are configured to receive a plug-in card1310 and 1312. The bus bridge circuit 1304 may be, for example, aNorthbridge, Southbridge or other suitable bridge circuit that includesfor example, the transceivers necessary to communicate via a PCIExpress™ communication link, or any other suitable link. In thisexample, there is no graphics processing circuitry necessary since thegraphics processor may be on one of the plug-in cards 1310 or 1312. Thiscan result in a smaller electronic device 1300 which still facilitateshigh speed video communication through the connector 100. As such,standard PCI Express™ cards may be plugged into the slots 1306 and 1308but a unique connector such as connector 100 is utilized to connect withanother electronic device such as a device with a host CPU, for example.

FIG. 30 illustrates another electronic device 1400 that instead ofutilizing standard bus slot connectors 1306 and 1308, utilizesconnectors 100 so that additional electronic devices such as that shownin FIG. 25 (device 904) may be suitably connected to the hub device1400. Also in this example, there is no need for A/C connector since thepower for the PCI bridge circuit 1304 would be provided by a downstreamdevice through a power connection in parallel to the connector 100. Asalso shown, a non-differential bus 1410 may also be employed between theelectronic devices 1904 if desired to provide a direct communicationlink between the devices as opposed to going through the bus bridgecircuit 1304. With the multiple graphics processors in the electronicdevices 1904, parallel graphics processing or video processing may beemployed if desired.

The device 1400 serves as an electronic hub device. It includes aplurality of divided multi connector element differential bus connectors100 that are coupled to the bridge circuit 1304. Each of the otherelectronic devices 1904 include an A/C input but also include dividedmulti connector element differential bus connectors 100. Displays mayalso be coupled so that output from the electronic circuitry may beprovided to corresponding displays. The bus connection 1410 between thegraphics processing circuitry of each external electronic device isdifferent than the bus through the divided multi connector elementdifferential bus connector. The displays display frames generated by thegraphics processing circuitry from one or both of the electronic devices1904.

Referring again to FIG. 25, the electronic device 904 includes the localframe buffer 930 that is coupled to the graphics processing circuitry414. The graphics processing circuitry 414 (e.g., one or more graphicsprocessors 933 or 934) generates and stores display frames in the localframe buffer 930 for the host device which is external to the housing ofdevice 904, in response to data received from the host device via thedivided multi-connector element differential bus connector 100. Theelectronic circuitry 414 is operative to communicate the display framesfrom the frame buffer 930 to the other device 902 through the dividedmulti-connector element differential bus connector 100. The datareceived from the other device may include, for example, drawingcommands sent by CPU 920 communicated via the multilane cable andconnector system 100, 500, 502. Other data may include, for example,video data such as compressed image information such as MPEG, JPEG, orother video compressed information which is then suitably decompressedand processed by the electronic circuitry 414 to generate display framesthat are stored in the frame buffer 930 and subsequently sent upstreamto be stored in the frame buffer 923 of the host device so that it iscopied therein and then displayed by a display engine, such as a portionof the graphics processor 922 as known in the art and displayed on thedisplay of the host device via, for example, the LVDS bus, or in anyother suitable fashion.

As such, the graphics processing circuitry 933 or 934 is operative tocommunicate with the processor 920 (and/or 922) in the host device andthe graphics processing circuitry 933 or 934 may receive drawingcommands or other data from the processor 920 and communicate generatedframes of the display data to the host device for display by the hostdevice. In this example, the graphics processing circuitry 414 or 933and 934 uses the plurality of differential signaling lanes of thedifferential links provided via the divided multi-connector elementdifferential bus connectors 100. As such, the electronic circuitry 414may generate frames for display on display 950 or may provide copies ofdisplay frames from its local frame buffer 930 to be displayed by thehost device on a display coupled to the host device. As such,independent units such as unit 904 with its own AC power source canrender an image into its local frame buffer and send the completed imageto a host frame buffer via the multilane PCI Express link via the uniqueconnectors 100. The host's display engine displays the copied image fromits frame buffer to a display device. No rendering (e.g., generation ofa frame based on drawing commands and/or video information) needs to bedone in the host device so minimal power is consumed in the host device.In addition, reuse of the PCI Express lanes in an upstream direction isprovided to provide peer to peer transfer of each frame from the unit904 to the host unit. In operation, the graphics processing circuit 933or 934 (or both) send only the number of frames needed by the hostdevice at a maximum rate compliant with the host display refresh rate ofthe displays that are being connected to the host. This may be, forexample, sixty frames per second for laptops if the host device is alaptop. Frame rate regulation may be carried out in an number of ways inorder to avoid saturation of the PCI Express bus by sending more displayframe information than can be displayed by the host. Synchronizing ofthe frame data is desirable to match the display rate of the laptop orhost device. Different synchronization mechanisms may be used such aspeer-to-peer writes from the unit 904 to the host with handshakingbetween the two units as necessary to indicate when the host is readyfor the next frame of data or by peer-to-peer reads from the unit 904initiated directly by the host when the host needs a new frame ofdisplay data, independent of additional handshaking between the unitsand therefore enhancing response time As such, the unit 904 generatesframes and reuses bus lanes in an upstream direction to send entireframes to a host which stores copies of the frames in its frame bufferand only displays the frames on the host display device. Otheradvantages will be recognized by those of ordinary skill in the art.

FIG. 31 illustrates one example of a method that may be carried out bymultiple graphics processors and corresponding logic in any suitablearchitecture. As shown in block 1500, the method may begin with a userbeing prompted by a driver application executing on a CPU to allow auser to select a low power mode for a graphics processor or otherportion of a system. As shown in block 1502, the method includesreducing power of a first GPU, such as a GPU in a host device or othersuitable GPU, by disabling or otherwise not using the rendering enginebut leaving the display engine of the GPU operational. For example,graphics processors are known that allow subsystems thereon to beselectively controlled for power reduction purposes. As known in theart, a graphics processor may include a rendering engine which generatesthe frames based on 3D commands and/or generating video frames based oncompressed video or other video source information. A display engineportion of the GPU reads the completed frame out of the frame buffer anddisplays it on one or more displays. The method includes leaving thedisplay engine on in the GPU so that it is still able to display framesthat are stored in the frame buffer corresponding to the first GPU, butthe rendering engine is in a reduced power state and preferably in astate that does not allow rendering so that maximum power reduction isprovided.

The method includes, as shown in block 1504 and as noted above,rendering a display frame by another graphics processor and storing therendered frame in its local frame buffer. This may be done, for example,by receiving suitable data via the communication path between theprocessors such as shown in FIG. 25 via the connector 100 anddifferential bus. However, any suitable link can be used. As shown inblock 1506, the method includes copying the rendered frame from thelocal frame buffer of the second GPU to the local frame buffer of thefirst GPU as described above under control of, for example, the driverexecuting on the host CPU. However, the synchronization scheme as notedabove may be any suitable synchronization scheme and a push or pullscheme may be used to cause the copying to occur. As shown in block1507, the process is completed for each frame that is rendered by thesecond GPU.

As shown in block 1508, the method includes displaying the copied framefrom the second GPU frame buffer using the display engine of the firstGPU since the copied frame is now located in the frame buffer of the GPUwhose rendering engine is effectively shut down but whose display engineis operational. This is done while the rendering engine is in thereduced power state. In one example the operations shown in blocks 1504,1506 and 1508 are all performed while the rendering engine of the firstGPU is in the reduced power state thereby maximizing power savings andreducing thermal output.

The method as noted may be carried out by the first and second devicesshown in FIG. 25 wherein each device includes at least one graphicsprocessor and corresponding frame buffer. In addition, for the secondGPU to render a frame, it receives data such as drawing commands orvideo processing commands from the second device since the renderingengine in the first graphics processor is not employed.

The graphics processor 933 for example in the device 904 renders adisplay frame in response to a rendering engine of another graphicsprocessor being in a reduced power state and stores the rendered framein a corresponding frame buffer 930. Logic, that may be incorporated forexample as part of the electronic circuitry 414 causes copying of therendered frame from the corresponding frame buffer to the frame bufferof the other graphics processor 922 and 923 in response to the renderingengine of the other graphics processor being in a reduced power state.As noted above, the logic may cause copying based on a request by thedriver executing on a CPU to request copying of the information from theframe buffer 930 to the frame buffer 923 or by a request from one of theseveral graphics processors. Alternatively, the graphics processor anddevice 904 may simply output a frame that is rendered once it iscomplete to the frame buffer 923. Any suitable copying scheme may beused.

It will be recognized that any suitable architecture may be used thatemploys any suitable communication path between the multiple graphicsprocessors. For example the graphics processors (e.g., cores) may beco-located on a same printed circuit board, may be on separate boards inthe same device or may be in separate devices as shown in the example ofFIG. 25.

The above detailed description of the invention and the examplesdescribed therein have been presented for the purposes of illustrationand description only and not by limitation. It is therefore contemplatedthat the present invention cover any and all modifications, variationsor equivalents that fall within the spirit and scope of the basicunderlying principles disclosed above and claimed herein.

What is claimed is:
 1. A method comprising: reducing power of arendering engine of a first graphics processor and leaving a displayengine of the first graphics processor capable of outputting displayframes from a corresponding first frame buffer to a display; rendering adisplay frame by a second graphics processor while the rendering engineof the first graphics processor is in a reduced power state; storing therendered frame in a corresponding second frame buffer of the secondgraphics processor; copying the rendered frame from the second framebuffer to the first frame buffer; and displaying the copied frame in thefirst frame buffer on a display while the rendering engine of a firstgraphics processor is in the reduced power state.
 2. The method of claim1 wherein copying the rendered frame from the second frame buffer to thefirst frame buffer comprises communicating the rendered frame to thefirst frame buffer via a differential communication bus.
 3. The methodof claim 1 wherein the reduced power state of the rendering engine ofthe first graphics processor is a low power state such that therendering engine is unable to render a display frame.
 4. A systemcomprising: a first device comprising: a first graphics processor thatcomprises at least a rendering engine and a display engine; and acorresponding first frame buffer, operatively coupled to the firstgraphics processor, operative to store rendered frames generated by therendering engine, the first device also being operative to reduce powerof the rendering engine of the first graphics processor and leave thedisplay engine of the first graphics processor capable of outputtingdisplay frames from the corresponding first frame buffer; and a seconddevice, in communication with the first device and comprising: a secondgraphics processor and corresponding second frame buffer, the secondgraphics processor operative to render a display frame while therendering engine of the first graphics processor is in a reduced powerstate and store the rendered frame in the corresponding second framebuffer of the second graphics processor, the second device operative tocopy the rendered frame from the second frame buffer to the first framebuffer of the second device; and the display engine in the firstgraphics processor of the first device operative to display the copiedframe in the first frame buffer on a display while the rendering engineof a first graphics processor is in the reduced power state.
 5. Thesystem of claim 4 wherein the first and second graphics processors arelinked by a differential communication bus and wherein copying therendered frame from the second frame buffer to the first frame buffercomprises communicating the rendered frame to the first frame buffer viathe differential communication bus and wherein rendering commands arereceived by the second device from the first device via the differentialcommunication bus.
 6. An apparatus comprising: a graphics processor andcorresponding frame buffer, the graphics processor operative to render adisplay frame in response to a rendering engine of another graphicsprocessor being in a reduced power state and operative to store therendered frame in the corresponding frame buffer, logic operative tocause copying of the rendered frame from the corresponding frame bufferto a frame buffer of another graphics processor in response to therendering engine of the other graphics processor being in a reducedpower state; and the display engine in the first graphics processor ofthe first device operative to display the copied frame in the firstframe buffer on a display while the rendering engine of a first graphicsprocessor is in the reduced power state.
 7. The apparatus of claim 6wherein the logic is incorporated in the graphics processor and whereinthe first and second graphics processors perform a handshaking operationto indicate when the first graphics processor is ready to receive a nextframe from the second graphics processor.
 8. The apparatus of claim 6wherein the logic is incorporated in the graphics processor and whereinthe first graphics processor reads a next frame from the second framebuffer of the second graphics processor.